By employing Wafer-level-chip-size-packaging (WLCSP) technology, a whole wafer may be diced into separated chips after it is packaged and tested. The packaged chip may have dimensions exactly the same as its dimensions before being packaged. WLCSP has revolutionized conventional packaging modes using, for example, ceramic leadless chip carriers or organic leadless chip carriers, and complies with the increasing requirements for lighter, smaller, shorter, thinner and cheaper microelectronic product. Chips packaged using WLCSP may have highly minimized dimensions. Manufacturing costs of chips may be tremendously reduced with the reduction of chip size and upsizing of wafers. WLCSP enables the integration of IC design, wafer manufacturing, packaging and testing, thereby becomes a hot spot in current packaging field and a feature trend.
Chinese patent application No. 200610096807.5 discloses a packaging method based on WLCSP, mainly including steps as follows.
As shown FIG. 1, a semiconductor wafer 1 is adhered with a first glass substrate 2. The semiconductor wafer 1 and the first glass substrate 2 may have the same dimensions. Therefore, devices formed on a surface of the semiconductor wafer 1 is covered and protected by the first glass substrate 2 during an initial stage of the packaging, thereby reducing external pollutions and damages.
As shown in FIG. 2, the semiconductor wafer 1 is thinned from its hack side which is opposite to the first glass substrate 2. By employing a lithographic process and a plasma etching process to selectively etch the wafer from the back side, a plurality of V-shaped grooves to be used as cutting trails are formed, partially exposing chip bonding pads 11 (i.e., chip electrodes).
As shown in FIG. 3, the V-shaped grooves are filled with an insulation material. Further, a second glass substrate 3 and a solder mask 4 are pressed and adhered onto the backside of the wafer. The second glass substrate 3 is used to support the semiconductor wafer 1. The solder mask 4 featured with electric and thermal insulation is used to provide mechanical buffer in a following mechanical slicing process, thereby protecting the semiconductor wafer 1.
As shown in FIG. 4, a mechanical slicing process is performed at the V-shaped grooves' former positions without separating the chips, thus new V-shaped grooves used as slicing trails of the wafer are formed. Besides, the chip bonding pads 11 are exposed from sidewalls of the new V-shaped grooves.
As shown in FIG. 5, external leads 12 are formed using electroplating technology. Each of the external leads 12 has one end connected with the chip bonding pads 11 in the new V-shaped grooves, and the other end extending to the back side of the wafer. In such ways, the chip bonding pads 11 are electrically connected to the back side of the wafer through the external leads 12.
As shown FIG. 6, an insulation protecting layer 14 is selectively formed on the back side of the wafer, where the external leads 12 are partially exposed. Soldering bumps 15 are formed on the exposed external leads 12. The wafer is sliced along the new V-shaped grooves on its back side, thereby forming separated chips. Thereafter, the separated chips are packaged in shells to complete the packaging.
Current WLCSP methods have following drawbacks. During the formation of the external leads 12 using the electroplating process, metal may be precipitated from the slicing trails (e.g., the V-shaped grooves described above) due to the electroplating processes. As a result, short circuit failure may occur between connecting lines. Furthermore, sidewalls of the separated chips, i.e., the sidewalls of the V-shaped grooves, are exposed to the outer environment, where damages may occur during the shell packaging. As a result, external leads may be broken, and the chip yield may be affected.